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SVTB技术培训

  • 分类:培训信息
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  • 发布时间:2009-02-10 17:34
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【概要描述】

SVTB技术培训

【概要描述】

  • 分类:培训信息
  • 作者:
  • 来源:
  • 发布时间:2009-02-10 17:34
  • 访问量:
详情
天津市IC设计公共服务平台暨天津市IC设计技术培训中心、天津市集成电路行业协会与美国Synopsys公司联合举办SystemVerilog Testbench(SVTB)技术培训。
 
培训 时间: 2009年2月18日——2月20日
会议地点:天津市集成电路设计公共服务平台培训室(天津市高新产业园区海泰发展六道6号海泰绿色产业基地G座九层)
招生对象:各集成电路设计公司工程师、各高校有志于涉足IC产业的研究生、科研院所、企业及社会有志于集成电路设计的工程技术人员,约40人。
报名时间:即日起至2009年2月16日,名额有限,报满为止,周一至周五工作时间。
联 系 人:天津大学综合实验楼808 史再峰 
天津市高新产业园区海泰发展六道6号海泰绿色产业基地G座九层 王金龙、陈天翔      
联系电话:022-85689008
收费标准:1000元/人
培训内容:
SystemVerilog Testbench
Overview
In this intensive, three-day course, students will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS.This course is a hands-on workshop that reinforces the verification concepts taught in lecture through a series of labs. At the end of this class,  students should have the skills required to write an object-oriented SystemVerilog testbench to verify a device under test with coverage-driven random stimulus using VCS. Students will first learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT). Next the workshop will explain how the intuitive object-oriented technology in SystemVerilog testbench can simplify verification problems. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow the students to assess the percentage of functionality covered either dynamically or through the use of generated reports. To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.
> Objectives
> At the end of this workshop the student should be able to:
>  *   Build a SystemVerilog verification environment
>  *   Develop a stimulus generator to create constrained random test stimulus
>  *   Develop device driver routines to drive DUT input with stimulus from generator
>  *   Develop device monitor routines to sample DUT output
>  *   Develop self-check routines to verify correctness of DUT output
>  *   Abstract DUT stimulus as data objects
>  *   Execute device drivers, monitors and self-checking routines concurrently
>  *   Communicate among concurrent routines using events, semaphores and mailboxes
>  *   Develop functional coverage to measure completeness of test
> Audience Profile
> Design or Verification engineers who write SystemVerilog testbenches at the block or chip level.
> Prerequisites
> To benefit the most from the material presented in this workshop, students should have:
>
>  *   A basic understanding of digital IC design
>  *   Familiarity with UNIX workstations running X-windows
>  *   Familiarity with vi, emacs, or other UNIX text editors
> Course Outline
>
>  *   Introduction
>  *   The Device Under Test
>  *   SystemVerilog Verification Environment
>  *   SystemVerilog Testbench Language Basics
>  *   Driving and Sampling DUT Signals
>  *   Managing Concurrency in SystemVerilog
>  *   Object Oriented Programming: Encapsulation
>  *   Object Oriented Programming: Randomization
>  *   Object Oriented Programming: Inheritance
>  *   Inter-Thread Communications
>  *   Functional Coverage
>  *   SystemVerilog VMM preview
> Synopsys Tools Used
>
>  *   VCS 2006.06 – SP2
课程安排:
Day1: 
                1. The Device Under Test (DUT)
                2. SystemVerilog Verification Environment
                3. SystemVerilog Language Basics
                4. Drive and Sample DUT Signals
Day2:
                1. Concurrency
                2. Object Oriented Programming (OOP) – Encapsulation
                3. Object Oriented Programming (OOP) – Randomization
Day3:
                1. Object Oriented Programming (OOP) – Inheritance
                2. Inter-Thread Communications
                3. Functional Coverage
                4. SystemVerilog VMM Preview
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